Prior art bipolar transistors, such as that illustrated in FIG. 8, have a number of layers of conductors and insulators in the vicinity of the active elements of the transistor. Interconnection lines must cross a step to enter an aperture above an emitter to make contact with the transistor electrode at the bottom of the aperture. The smaller the dimensions of the transistor, the greater the aspect ratio or ratio of height to width of the emitter aperture. The greater this aspect ratio, or the greater the step, the more prone the transistor is to suffer failure for a number of reasons.
One reason is that of metal penetration and stress-induced failure due to nonconformal metal/dielectric deposition on severe topography (meaning relatively high steps). Another reason is that of device degradation of transistors having small emitters due to non-uniform doping of the emitter because of interference from a sidewall in reason is the formation of a short circuit between the emitter and the base due to nonconformal sidewall deposition. Yet another problem is variability in the size of the emitter opening recess due to the lack of an etch stop of the material (poly in the prior art) covering the base.
The art has employed a number of approaches to reduce the topography of bipolar transistors. Considerations include the interplay between chemical and mechanical considerations in the assembly of a set of layers and electrical considerations in the operation of the transistor. To improve planarity, the basic problem to be addressed is the reduction of thickness of dielectric and/or a reduction in the number of layers. One example of a prior art transistor is illustrated in FIG. 8, showing a structure formed by a two layer polysilicon (poly) process, in which a base connector is formed in poly 1 above the local surface of the wafer. The poly has to extend over the field oxide because of alignment considerations, so that the set of layers is: field oxide, poly 1, and two layers of dielectric.
Another approach is illustrated in U.S. Pat. No. 4,824,799, in which a step of codeposition of polysilicon and epitaxial monocrystalline silicon (epi) is used, with the epi filling a trench etched in a field insulator to provide the starting material for the transistor and the poly being oxidized to provide an interlayer dielectric.